Description: SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中,前9列为开销字节,它包含了很多重要的信息,本程序为SDH开销的接收处理,查找帧头,分频,勤务话字节E1异步fifo。可拆为三段源代码,不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhead bytes, it contains a lot of important information, the procedures for receiving SDH overhead processing, search header, sub-frequency ,勤務if E1 asynchronous byte fifo. Removable for three source code, I do not know the three procedures can be arrived Platform: |
Size: 6144 |
Author:韩冰 |
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Description: 异步FIFO实例,精通verilog hdl中的例子,供大家学习-Asynchronous FIFO instance, in the example verilog hdl proficiency for all learning Platform: |
Size: 2048 |
Author:林 |
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Description: The SC16C752B is a dual Universal Asynchronous Receiver/Transmitter (UART) with
64-byte FIFOs, automatic hardware/software flow control, and data rates up to 5 Mbit/s
(3.3 V and 5 V). The SC16C752B offers enhanced features. It has a Transmission Control
Register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during
hardware and software flow control. With the FIFO Rdy register, the software gets the
status of TXRDY/RXRDY for all four ports in one access. On-chip status registers provide
the user with error indications, operational status, and modem interface control. System
interrupts may be tailored to meet user requirements. An internal loopback capability
allows on-board diagnostics. Platform: |
Size: 160768 |
Author:刘伟 |
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Description: 这是一个异步fifo的Verilog 代码,该代码的功能是实现异步的first in first out-This is an asynchronous fifo in the Verilog code, the code' s function is to achieve asynchronous first in first out Platform: |
Size: 1024 |
Author:Yongjie |
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Description: 用verilog实现异步FIFO,代码中有两个模块,使用时时注意顶层模块和底层模块,用quartus2即可打开直接使用。
-Asynchronous FIFO, with verilog code has two modules, using the constant attention of top-level module and bottom module with quartus2 to open. Platform: |
Size: 2048 |
Author:zcl1233 |
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Description: verilog编写的异步fifo源代码,asyn_fiifo.v为顶层,调用其他四个文件,
-verilog prepared the the asynchronous fifo source code, asyn_fiifo.v for the top floor, calling the other four documents, Platform: |
Size: 2048 |
Author:mmzz3211 |
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Description: 同步与异步FIFO的verilog实现,包括源代码,testbench,测试以及综合通过,还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references Platform: |
Size: 1715200 |
Author:gt |
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